HFT Sidecar

For ultra-low-latency processes that cannot embed the SDK (trading systems, FPGA interfaces, kernel-bypass networking), the nerve-sidecar daemon reads from a POSIX shared memory ring buffer and forwards frames to the QUIC pipeline. Zero-copy, 100 kHz polling.

When to Use

• HFT / Market Data: Your trading process cannot tolerate any jitter from QUIC networking or memory allocation
• FPGA / DMA: Hardware writes directly to shared memory — no SDK needed in the critical path
• Multi-language: Non-Rust processes (C, C++, Python) write to shared memory; the sidecar handles transport

Shared Memory Layout

The ring buffer uses a #[repr(C)] header followed by fixed-size frame slots.

Ring Header

Frame Header

Configuration

Running

# Start the sidecar daemon
cargo run --release --bin nerve-sidecar

# With custom shared memory name
nerve-sidecar --shm-name my_trading_ring --endpoint 10.0.0.5:4433

Writing from C/C++

// Open shared memory
int fd = shm_open("/nerve_ring", O_RDWR, 0666);
void* ptr = mmap(NULL, SHM_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);

// Write a frame
RingHeader* hdr = (RingHeader*)ptr;
uint64_t slot = atomic_load(&hdr->write_pos) % (hdr->capacity / hdr->frame_size);
FrameHeader* frame = (FrameHeader*)(ptr + sizeof(RingHeader) + slot * hdr->frame_size);
frame->schema_id = 0x00000002;
frame->payload_len = payload_size;
frame->sequence = seq++;
memcpy(frame + 1, payload, payload_size);
atomic_fetch_add(&hdr->write_pos, 1);